Darshika G. Perera

发表

Kin Fun Li, Darshika G. Perera, 2009, 2009 Eighth IEEE International Conference on Dependable, Autonomic and Secure Computing.

A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware

Kin Fun Li, Darshika G. Perera, K. F. Li, 2019, Int. J. Embed. Syst..

Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms

Darshika G. Perera, Arkan Alkamil, D. Perera, 2019, 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

An Optimized FPGA-Based Hardware Accelerator for Physics-Based EKF for Battery Cell Management

M. Scott Trimboli, Darshika G. Perera, Anne K. Madsen, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware

Kin Fun Li, Darshika G. Perera, 2019, Int. J. Embed. Syst..

Efficient embedded architectures for fast-charge model predictive controller for battery cell management in electric vehicles

Darshika G. Perera, Anne K. Madsen, D. Perera, 2018, EURASIP J. Embed. Syst..

Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis

Darshika G. Perera, S. Navid Shahrouzi, S. N. Shahrouzi, 2019, Microprocess. Microsystems.

An efficient embedded multi-ported memory architecture for next-generation FPGAs

Darshika G. Perera, S. Navid Shahrouzi, S. N. Shahrouzi, 2017, 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications

Darshika G. Perera, D. Perera, 2015, FPGAworld.

Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs

Darshika G. Perera, S. Navid Shahrouzi, 2018, 2018 31st IEEE International System-on-Chip Conference (SOCC).

Analysis of Computational Models and Application Characteristics Suitable for Reconfigurable FPGAs

Kin Fun Li, Darshika G. Perera, K. F. Li, 2015, 2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC).

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

Darshika G. Perera, Arkan Alkamil, D. Perera, 2020, IEEE Access.

An Investigation of Chip-Level Hardware Support for Web Mining

Kin Fun Li, Darshika G. Perera, 2007, 21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07).

Analysis of single-chip hardware support for mobile and embedded applications

Kin Fun Li, Darshika G. Perera, K. F. Li, 2013, 2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM).

An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices

Darshika G. Perera, Mokhles A. Mohsin, D. Perera, 2018, HEART.

A fast and scalable FPGA-based parallel processing architecture for K-means clustering for big data analysis

Darshika G. Perera, Ramprasad Raghavan, D. Perera, 2017, 2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM).

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Darshika G. Perera, S. Navid Shahrouzi, S. N. Shahrouzi, 2017, EURASIP J. Embed. Syst..

Embedded hardware solution for principal component analysis

Kin Fun Li, Darshika G. Perera, 2011, Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

A Hardware Collective Intelligence Agent

Kin Fun Li, Darshika G. Perera, 2013, Trans. Comput. Collect. Intell..

An efficient FPGA-based memory architecture for compute-intensive applications on embedded devices

Darshika G. Perera, S. Navid Shahrouzi, 2017, 2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM).

A Quad Joint Relational Feature for 3D Skeletal Action Recognition with Circular CNNs

Darshika G. Perera, Kiran Kumar Eepuri, Maddala Teja Kiran Kumar, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

A Fast and Secure Pipelined Barrel Processor for Safety-Critical Applications for Real-Time Operating Systems

Darshika G. Perera, Mong Tee Sim, 2019, 2019 IEEE 10th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON).

FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications

Kin Fun Li, Darshika G. Perera, K. F. Li, 2011, 2011 International Conference on P2P, Parallel, Grid, Cloud and Internet Computing.

Parallel Computation of Similarity Measures Using an FPGA-Based Processor Array

Kin Fun Li, Darshika G. Perera, K. F. Li, 2008, 22nd International Conference on Advanced Information Networking and Applications (aina 2008).

HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools

Darshika G. Perera, S. Navid Shahrouzi, 2019, 2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM).

An Efficient FPGA-Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms

Darshika G. Perera, Srikanth Ramadurgam, D. Perera, 2021, Electronics.

Intelligent Cognitive Radio Architecture Applying Machine Learning and Reconfigurability

Jari Nurmi, Darshika G. Perera, 2021, 2021 IEEE Nordic Circuits and Systems Conference (NorCAS).

A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices

Darshika G. Perera, D. Perera, Srikanth Ramadurgam, 2023, 2023 IEEE International Symposium on Circuits and Systems (ISCAS).