R. Rupani

Modeling of Gate Leakage, Floating Body Effect, and History Effect in 32nm HKMG PD-SOI CMOS

Y. Deng, J. Johnson, S. Springer, 2010 .

MATHEMATICAL TECHNIQUE IMPROVES DIRECTIONAL WELL-PATH PLANNING

P. V. R. Suryanarayana, R. C. Mccann, R. L. Rudolf, 1998 .

Midwave infrared type-II InAs∕GaSb superlattice detectors with mixed interfaces

Elena Plis, S. Krishna, R. A. Rupani, 2006 .

Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications

D. Daley, L. Wagner, S. Narasimha, 2012, 2012 Symposium on VLSI Technology (VLSIT).