S. Yin

发表

An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video

Shouyi Yin, Shaojun Wei, Weilong Zhang, 2013, Science China Information Sciences.

A Reliable Physical Unclonable Function Based on Differential Charging Capacitors

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Power Efficient Design and Implementation of a Novel Constant Correction Truncated Multiplier

Leibo Liu, S. Yin, Shaojun Wei, 2011 .

Performance Comparison of Multipath Routing Algorithms for TCP Traffic

Xiaokang Lin, Guangyi Liu, Shouyi Yin, 2003 .

CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process

Leibo Liu, S. Yin, Shaojun Wei, 2022, ISCA.

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems

Jie Han, Honglan Jiang, Leibo Liu, 2022, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Traffic-aware Routing for RTC in Wireless Multi-hop Networks

Xiaokang Lin, Shouyi Yin, Yongqiang Xiong, 2007 .

FAQS: Communication-efficient Federate DNN Architecture and Quantization Co-Search for personalized Hardware-aware Preferences

Leibo Liu, S. Yin, Shaojun Wei, 2022, ArXiv.

BR-CIM: An Efficient Binary Representation Computation-In-Memory Design

Leibo Liu, S. Yin, Shaojun Wei, 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention

Jingchuang Wei, Leibo Liu, S. Yin, 2023, IEEE Journal of Solid-State Circuits.

BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial Neural Network Accelerators

Ang Li, Leibo Liu, S. Yin, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Journal of Solid-State Circuits.

Traffic-aware routing for real-time communications in wireless multi-hop networks

Qian Zhang, Xiaokang Lin, Shouyi Yin, 2006, Wirel. Commun. Mob. Comput..

Traffic-aware routing for real time communications in wireless multi-hop networks

Qian Zhang, Xiaokang Lin, Shouyi Yin, 2006, IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC'06).

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Inf. Syst..

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

Yu Peng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Optimizing Spatial Mapping of Nested Loop for

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015 .

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications

Dong Wang, Chenchen Deng, Leibo Liu, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Inf. Syst..

Polyhedral model based mapping optimization of loop nests for CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

A reconfigurable multi-processor SoC for media applications

Wenjie Wang, Leibo Liu, Shouyi Yin, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Compiler Framework for Reconfigurable Computing Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, IEICE Trans. Electron..

Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System

Hui Gao, Leibo Liu, Shouyi Yin, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, FPGA.

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture

Rui Shi, Leibo Liu, Shouyi Yin, 2015, IEICE Trans. Inf. Syst..

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration

Victor Y. Chen, Dong Wang, Leibo Liu, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast and low-power behavior analysis on vehicles using smartphones

Shouyi Yin, Peng Ouyang, Xiaoqing Xu, 2017, 2017 6th International Symposium on Next Generation Electronics (ISNE).

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Dong Wang, Jun Yang, Leibo Liu, 2015, IEEE Transactions on Multimedia.

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Inf. Syst..

An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning

Shouyi Yin, Dandan Song, Peng Ouyang, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Circuits and Systems for Video Technology.

Scale Invariant Feature Transform algorithm based on a reconfigurable architecture system

Hui Gao, Leibo Liu, Shouyi Yin, 2012, 2012 8th International Conference on Computing Technology and Information Management (NCM and ICNIT).

Prediction-based routing for real time communications in wireless multi-hop networks

Qian Zhang, Xiaokang Lin, Shouyi Yin, 2006, QShine '06.

Multipath minimum energy routing in ad hoc network

Xiaokang Lin, Shouyi Yin, Xiaokang Lin, 2005, IEEE International Conference on Communications, 2005. ICC 2005. 2005.

Adaptive load balancing in mobile ad hoc networks

Xiaokang Lin, Shouyi Yin, Xiaokang Lin, 2005, IEEE Wireless Communications and Networking Conference, 2005.

MALB: MANET adaptive load balancing

Xiaokang Lin, Shouyi Yin, Xiaokang Lin, 2004, IEEE 60th Vehicular Technology Conference, 2004. VTC2004-Fall. 2004.

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Yangdong Deng, Shouyi Yin, Jianfeng Zhu, 2019, ACM Comput. Surv..

Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips

Leibo Liu, S. Yin, Shaojun Wei, 2023, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures

Yangdong Deng, Shouyi Yin, Xiaowei Jiang, 2021, IEEE Transactions on Parallel and Distributed Systems.

FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning

Yang Wang, Shouyi Yin, Ning Li, 2021, IEEE Journal of Solid-State Circuits.

Efficient Scheduling of Irregular Network Structures on CNN Accelerators

Shouyi Yin, Shibin Tang, Shaojun Wei, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Architecture, challenges and applications of dynamic reconfigurable computing

Shouyi Yin, Yanan Lu, Shaojun Wei, 2020, Journal of Semiconductors.

Towards Efficient Compact Network Training on Edge-Devices

Shouyi Yin, Fengbin Tu, Shaojun Wei, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions

Shouyi Yin, Weiwei Wu, Fengbin Tu, 2019, 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS).

A Computing Efficient Hardware Architecture for Sparse Deep Neural Network Computing

Youguang Zhang, Shouyi Yin, Shaojun Wei, 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Journal of Solid-State Circuits.

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Atomic Dataflow based Graph-Level Workload Orchestration for Scalable DNN Accelerators

Leibo Liu, S. Yin, Shaojun Wei, 2022, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

A fast and power efficient architecture to parallelize LSTM based RNN for cognitive intelligence applications

Shouyi Yin, Shaojun Wei, Peng Ouyang, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization

Xin Si, Shouyi Yin, Shaojun Wei, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs

Leibo Liu, S. Yin, Shaojun Wei, 2020, 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC).

24.4 Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation

Jun Yang, Yan Liu, Shouyi Yin, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

FP-BNN: Binarized neural network on FPGA

Wayne Luk, Leibo Liu, Shouyi Yin, 2018, Neurocomputing.

STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction

Yang Wang, Shouyi Yin, Feng Xiong, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation

Yang Wang, Shouyi Yin, Xinhan Lin, 2021, 2021 Symposium on VLSI Circuits.

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

LCP: a Layer Clusters Paralleling mapping method for accelerating Inception and Residual networks on FPGA

Xiangyu Li, Leibo Liu, Shouyi Yin, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection

Shouyi Yin, Sheng Zhou, Shaojun Wei, 2020, IEEE Journal of Solid-State Circuits.

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms

Bo Wang, Chenchen Deng, Leibo Liu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network

Youguang Zhang, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Magnetics.

Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform

Shouyi Yin, Cong Liu, Yang Hu, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient Hardware Architecture of Softmax Layer in Deep Neural Network

Shouyi Yin, Shaojun Wei, Binren Tian, 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

Transformer with Bidirectional Decoder for Speech Recognition

Shouyi Yin, Xi Chen, Songyang Zhang, 2020, INTERSPEECH.

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration

Yufei Ding, Leibo Liu, S. Yin, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory

Yangdong Deng, Shouyi Yin, Jiawei Wang, 2019, MICRO.

PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement

Shouyi Yin, Peng Ouyang, Zihang Jiang, 2020, ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes

L. Liu, Leibo Liu, S. Yin, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes

L. Liu, Leibo Liu, S. Yin, 2023, IEEE Journal of Solid-State Circuits.

16.1 MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers

Leibo Liu, S. Yin, Shaojun Wei, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

A 28nm 57.6TOPS/W Attention-based NN Processor with Correlative Computing-in-Memory Ring and Dataflow-reshaped Digital-assisted Computing-in-Memory Array

Ruiqi Guo, Yaojun Zhang, Leibo Liu, 2022, 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC).

7.7 CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction

Ruiqi Guo, Leibo Liu, S. Yin, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks

Bo Wang, Chenchen Deng, Shouyi Yin, 2017, IEEE Transactions on Information Forensics and Security.

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems

Chenchen Deng, Leibo Liu, Shouyi Yin, 2017, IEEE Transactions on Parallel and Distributed Systems.

Constructing Concurrent Data Structures on FPGA with Channels

Hui Yan, Leibo Liu, Shouyi Yin, 2019, FPGA.

A VLSI design of sensor node for wireless image sensor network

Xinkai Chen, Leibo Liu, Shouyi Yin, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation

Shouyi Yin, Pan Wang, Sheng Zhou, 2020, IEEE Transactions on Wireless Communications.

Battery-aware mapping optimization of loop nests for CGRAs

Yu Peng, Leibo Liu, Shouyi Yin, 2015, The 20th Asia and South Pacific Design Automation Conference.

Battery-Aware Loop Nests Mapping for CGRAs

Yu Peng, Leibo Liu, Shouyi Yin, 2015, IEICE Trans. Inf. Syst..

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems

Shouyi Yin, Sheng Zhou, Shaojun Wei, 2020, IEEE Transactions on Signal Processing.

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

Small-Footprint Keyword Spotting with Graph Convolutional Network

Shouyi Yin, Xi Chen, Peng Ouyang, 2019, 2019 IEEE Automatic Speech Recognition and Understanding Workshop (ASRU).

Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning

Jingchuang Wei, Leibo Liu, S. Yin, 2022, IEEE Journal of Solid-State Circuits.

16.4 TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration

Leibo Liu, S. Yin, Shaojun Wei, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

MapReduce inspired loop mapping for coarse-grained reconfigurable architecture

Leibo Liu, S. Yin, Shaojun Wei, 2014, Science China Information Sciences.

FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction

Leibo Liu, S. Yin, Shaojun Wei, 2023, ISCA.

Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning

Yang Wang, Shouyi Yin, Fengbin Tu, 2021, IEEE Journal of Solid-State Circuits.

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization

Ruiqi Guo, Meng-Fan Chang, Xin Si, 2023, IEEE Journal of Solid-State Circuits.

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration

Yufei Ding, Leibo Liu, S. Yin, 2023, IEEE Journal of Solid-State Circuits.

SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning

Leibo Liu, S. Yin, Shaojun Wei, 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.

HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning

Yang Wang, Shouyi Yin, Shaojun Wei, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent

Yangdong Deng, Shouyi Yin, Yifan Yang, 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

MSAM: A Multi-Layer Bi-LSTM Based Speech to Vector Model with Residual Attention Mechanism

Shouyi Yin, Dongdong Cui, Shaojun Wei, 2019, 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems

Leibo Liu, S. Yin, Shaojun Wei, 2023, IEEE Journal of Solid-State Circuits.

A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium

Shouyi Yin, Zhengdong Li, Leibo Liu, 2021, IACR Trans. Cryptogr. Hardw. Embed. Syst..

Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT

Chen Chen, Shouyi Yin, Shaojun Wei, 2020, IACR Trans. Cryptogr. Hardw. Embed. Syst..

A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems

Leibo Liu, S. Yin, Shaojun Wei, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Shouyi Yin, Leibo Liu, Shaojun Wei, 2021, IACR Trans. Cryptogr. Hardw. Embed. Syst..

CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture

Zhiwei Liu, Shouyi Yin, Zhaoshi Li, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

Chen Yang, Leibo Liu, S. Yin, 2014, Science China Physics, Mechanics & Astronomy.

Face Alignment With Expression- and Pose-Based Adaptive Initialization

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Multimedia.

A real-time time-consistent 2D-to-3D video conversion system using color histogram

Zhen Zhang, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Consumer Electronics.

A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, Sensors.

Real-time time-consistent 2D-to-3D video conversion based on color histogram

Zhen Zhang, Leibo Liu, Shouyi Yin, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration

Leibo Liu, S. Yin, Shaojun Wei, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory

Cong Xu, Yuan Xie, Jishen Zhao, 2019, IEEE Transactions on Parallel and Distributed Systems.

Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature

Yike Guo, Leibo Liu, Shouyi Yin, 2015, Sensors.

Efficient access scheme for multi-bank based NTT architecture through conflict graph

Bohan Yang, Leibo Liu, S. Yin, 2022, Design Automation Conference.

An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 Symposium on VLSI Circuits.

PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing

Leibo Liu, S. Yin, Shaojun Wei, 2022, IEEE Transactions on Circuits and Systems Part 1: Regular Papers.

A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration

Yike Guo, Leibo Liu, Shouyi Yin, 2016, IEEE Computer Architecture Letters.

A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing

Jingchuang Wei, Leibo Liu, S. Yin, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction

Shouyi Yin, Leibo Liu, Huiyu Mo, 2021, IEEE Journal of Solid-State Circuits.

TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs

Shouyi Yin, Yuyao Kong, Leibo Liu, 2021, IEEE Journal of Solid-State Circuits.

SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization

Yuan Xie, Leibo Liu, S. Yin, 2023, IEEE Transactions on Circuits and Systems Part 1: Regular Papers.

A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Symposium on VLSI Circuits.

A Multi-Task Hardwired Accelerator for Face Detection and Alignment

Hong Liu, Shouyi Yin, Qiang Li, 2020, IEEE Transactions on Circuits and Systems for Video Technology.

NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication

Shouyi Yin, Leibo Liu, Neng Zhang, 2020, IEEE Transactions on Computers.

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, J. Syst. Archit..

Optimization of Softmax Layer in Deep Neural Network Using Integral Stochastic Computation

Shouyi Yin, Shaojun Wei, Binren Tian, 2018, J. Low Power Electron..

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints

Jie Han, Leibo Liu, S. Yin, 2015, Science China Information Sciences.

Aggressive pipelining of irregular applications on reconfigurable hardware

Yao Wang, Yangdong Deng, Leibo Liu, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture

Chenchen Deng, Leibo Liu, Shouyi Yin, 2016, IEEE Transactions on Information Forensics and Security.

A High Precision Feature Based on LBP and Gabor Theory for Face Recognition

Shouyi Yin, Wei Xia, Peng Ouyang, 2013, Sensors.

Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays

Yiyu Shi, Yangdong Deng, Leibo Liu, 2018, IEEE Transactions on Parallel and Distributed Systems.

Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration

Shouyi Yin, Shaojun Wei, Jiangyuan Gu, 2018, IEEE Transactions on Parallel and Distributed Systems.

A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT

Youguang Zhang, Leibo Liu, Shouyi Yin, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation

Chunxiao Xing, Leibo Liu, Shouyi Yin, 2017, ACM Great Lakes Symposium on VLSI.

A fast and robust traffic sign recognition method using ring of RIBP histograms based feature

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE International Conference on Robotics and Biomimetics (ROBIO 2014).

A FAST Extreme Illumination Robust Feature in Affine Space

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 22nd International Conference on Pattern Recognition.

A Full Multicast Reconfigurable Non-blocking Permutation Network

Hui Li, Leibo Liu, Shouyi Yin, 2018, 2018 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC).

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation

Jie Han, Honglan Jiang, Leibo Liu, 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.

Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution

Yangdong Deng, Leibo Liu, Shouyi Yin, 2018, IEEE Computer Architecture Letters.