Ranjani Narayan

发表

REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress)

Kavitha T. Madhu, Tarun Singla, S. K. Nandy, 2017, CASES.

Multiprocessor system-on-chip for processing data in cloud computing

Ranjani Narayan, Arnab Kumar Biswas, S. K. Nandy, 2017 .

Design of a low power 64 point FFT architecture for WLAN applications

S. K. Nandy, Ranjani Narayan, S. Kala, 2013, 2013 25th International Conference on Microelectronics (ICM).

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Work-in-progress: REDEFINE – a case for WCET-friendly hardware accelerators for real time applications

Tarun Singla, Ranjani Narayan, Francois Neumann, 2017, 2017 International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES).

REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores

S. K. Nandy, Ranjani Narayan, Gopinath Mahale, 2016, IEEE Transactions on Parallel and Distributed Systems.

Using reconfigurable multi-core architectures for safety-critical embedded systems

Ranjani Narayan, Francois Neumann, Philippe Baufreton, 2016, 2016 IEEE/AIAA 35th Digital Avionics Systems Conference (DASC).

Applying Modified Householder Transform to Kalman Filter

Rainer Leupers, Ranjani Narayan, Anupam Chattopadhyay, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

REDEFINE: Runtime reconfigurable polymorphic ASIC

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, TECS.

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, ARC.

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform

S. K. Nandy, Ranjani Narayan, Prasenjit Biswas, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic

S. K. Nandy, Ranjani Narayan, Farhad Merchant, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

Framework for Enabling Highly Available Distributed Applications for Utility Computing

S. K. Nandy, Ranjani Narayan, J. Lakshmi, 2006, ISPA.

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2014, J. Syst. Archit..

Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture

S. K. Nandy, Ranjani Narayan, S. Kala, 2015, J. Low Power Electron..

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, 2009 IEEE International SOC Conference (SOCC).

A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks

S. K. Nandy, Ranjani Narayan, Tanmay Verma, 2015, 2015 28th International Conference on VLSI Design.

A Generic Graph-Oriented Mapping Strategy for a Honeycomb Topology

Ranjani Narayan, S. K. Nandy, Mythri Alle, 2010 .

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR)

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2018, ARC.

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2016, IEEE Transactions on Parallel and Distributed Systems.

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat

S. K. Nandy, Ranjani Narayan, Arnab Kumar Biswas, 2015, Circuits Syst. Signal Process..

Micro-Architectural support for High Availability of NoC-based MP-SoC

Ranjani Narayan, Francois Neumann, Philippe Baufreton, 2019, 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC).

Reducing scheduling overheads in dynamically reconfigurable processors (リコンフィギャラブルシステム)

Ranjani Narayan, Masahiro Fujita, S. K. Nandy, 2010 .

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE

Masahiro Fujita, S. K. Nandy, Ranjani Narayan, 2010, CASES '10.

A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Network-on-chip router attacks and their prevention in MP-SoCs with multiple Trusted Execution Environments

S. K. Nandy, Ranjani Narayan, Arnab Kumar Biswas, 2015, 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).

Reducing scheduling overheads in dynamically reconfigurable processors (VLSI設計技術)

Ranjani Narayan, Masahiro Fujita, S. K. Nandy, 2010 .

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Task Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architectures with an Application on Control of Propulsion System

Ranjani Narayan, Philippe Baufreton, Eric Feron, 2019, 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC).

Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture

S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan, 2010, 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

Compiling HPC Kernels for the REDEFINE CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

An Input Triggered Polymorphic ASIC for H.264 Decoding

S. K. Nandy, Ranjani Narayan, Mythri Alle, 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.

Synthesis of application accelerators on Runtime Reconfigurable Hardware

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design pdf

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2017, Parallel Process. Lett..

Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture

Masahiro Fujita, S. K. Nandy, Ranjani Narayan, 2011, ARC.

Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields

S. K. Nandy, Ranjani Narayan, Saptarsi Das, 2011, ICETE.

A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture

Ranjani Narayan, S. K. Nandy, Saptarsi Das, 2012 .

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design pdf

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2016, ArXiv.

Performance analysis of a multiprocessor machine based on data flow principles

Ranjani Narayan, V. Rajaraman, 1990 .

Energy aware synthesis of application kernels through composition of data-paths on a CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2017, Integr..

A method for flexible reduction over binary fields using a field multiplier

S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan, 2011, Proceedings of the International Conference on Security and Cryptography.

VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks

S. K. Nandy, Ranjani Narayan, Gopinath Mahale, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations

S. K. Nandy, Ranjani Narayan, Farhad Merchant, 2015, 2015 28th International Conference on VLSI Design.

Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization pdf

Rainer Leupers, S. K. Nandy, Ranjani Narayan, 2018, ArXiv.

A Framework for QoS Adaptive Grid Meta Scheduling

S. K. Nandy, Ranjani Narayan, J. Lakshmi, 2005, 16th International Workshop on Database and Expert Systems Applications (DEXA'05).

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture

Masahiro Fujita, S. K. Nandy, Ranjani Narayan, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, CASES '09.

High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit

S. K. Nandy, Ranjani Narayan, S. Kala, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array

S. K. Nandy, Ranjani Narayan, P. Sadayappan, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Hardware Solution for Real-Time Face Recognition

S. Bhattacharya, S. K. Nandy, Ranjani Narayan, 2015, 2015 28th International Conference on VLSI Design.

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

S. K. Nandy, Ranjani Narayan, Prasenjit Biswas, 2010, 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

Task allocation of safety-critical applications on reconfigurable multi-core architectures

S. K. Nandy, Ranjani Narayan, Francois Neumann, 2017, 2017 IEEE/AIAA 36th Digital Avionics Systems Conference (DASC).

Experimental Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architecture

S. K. Nandy, Ranjani Narayan, Francois Neumann, 2018, 2018 IEEE/AIAA 37th Digital Avionics Systems Conference (DASC).

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2015, 2015 IEEE International Symposium on Nanoelectronic and Information Systems.

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs

S. K. Nandy, Ranjani Narayan, Farhad Merchant, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Flexible resource allocation and management for application graphs on ReNÉ MPSoC

Ranjani Narayan, Anuj Rao, Saptarsi Das, 2016, PARMA-DITAM '16.

Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems

S. K. Nandy, Ranjani Narayan, S. Kala, 2014, 2014 Fifth International Symposium on Electronic System Design.

A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design

Rainer Leupers, Ranjani Narayan, Anupam Chattopadhyay, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders

S. K. Nandy, Ranjani Narayan, Mythri Alle, 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

A H.264 decoder: A design style comparison case study

S. K. Nandy, Ranjani Narayan, Hristo Nikolov, 2009, 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers.

An Incessantly Coherent Cache Scheme for SharedMemory Multithreaded

S. K. Nandy, Ranjani Narayan, 1994 .