Sergei Devadze

发表

Environment for the analysis of functional self-test quality in digital systems

Raimund Ubar, Sergei Kostin, Helena Kruus, 2014 .

Fast extended test access via JTAG and FPGAs

Raimund Ubar, Sergei Devadze, Artur Jutman, 2009, 2009 International Test Conference.

Web-Based Software Implementation of Finite State Machine Decomposition for Design and Education

Sergei Devadze, Margus Kruus, Alexander Sudnitson, 2001 .

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits

Raimund Ubar, Jaan Raik, Sergei Devadze, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

Combinational fault simulation in sequential circuits

Raimund Ubar, Sergei Devadze, Maksim Gorev, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Embedded synthetic instruments for Board-Level testing

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2012, 2012 17th IEEE European Test Symposium (ETS).

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure

Sergei Devadze, Artur Jutman, Konstantin Shibin, 2017, IEEE Design & Test.

On in-system programming of non-volatile memories

Sergei Devadze, Artur Jutman, Artjom Jasnetski, 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

Collaborative Distributed Computing in the Field of Digital Electronics Testing

Raimund Ubar, Sergei Devadze, Eero Ivask, 2010, BASYS.

Parallel exact critical path tracing fault simulation with reduced memory requirements

Raimund Ubar, Jaan Raik, Sergei Devadze, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

Reliable health monitoring and fault management infrastructure based on embedded instrumentation and IEEE 1687

Sergei Devadze, Artur Jutman, Konstantin Shibin, 2016, 2016 IEEE AUTOTESTCON.

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

Raimund Ubar, Jaan Raik, Sergei Devadze, 2005, EDCC.

Virtual reconfigurable scan-chains on FPGAs for optimized board test

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2015, 2015 16th Latin-American Test Symposium (LATS).

In-system programming of non-volatile memories on microprocessor-centric boards

Sergei Devadze, Artur Jutman, Artjom Jasnetski, 2014 .

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models

Raimund Ubar, Sergei Devadze, Artur Jutman, 2011, 2011 Asian Test Symposium.

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2016, J. Electron. Test..

Parallel X-fault simulation with critical path tracing technique

Raimund Ubar, Jaan Raik, Sergei Devadze, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Learning Digital Test and Diagnostics via Internet

Raimund Ubar, Sergei Devadze, Margus Kruus, 2007, Int. J. Online Eng..

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2018, 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Designing Reliable Cyber-Physical Systems

Jaan Raik, Hans G. Kerkhoff, Sergei Devadze, 2018 .

Run-time reconfigurable instruments for advanced board-level testing

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2016, 2016 IEEE AUTOTESTCON.

At-speed self-testing of high-performance pipe-lined processing architectures

Raimund Ubar, Jaan Raik, Sergei Devadze, 2013, 2013 NORCHIP.

Distributed approach for parallel exact critical path tracing fault simulation

Raimund Ubar, Sergei Devadze, Eero Ivask, 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

Collaborative Distributed Fault Simulation for Digital Electronic Circuits

Raimund Ubar, Sergei Devadze, Eero Ivask, 2010, IDC.

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits

Raimund Ubar, Jaan Raik, Sergei Devadze, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

Critical Path Tracing Based Simulation of Transition Delay Faults

Raimund Ubar, Jaan Raik, Sergei Devadze, 2014, 2014 17th Euromicro Conference on Digital System Design.

Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits

Raimund Ubar, Sergei Devadze, Eero Ivask, 2011, Scalable Comput. Pract. Exp..

FPGA-based synthetic instrumentation for board test

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2012, 2012 IEEE International Test Conference.

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs

Raimund Ubar, Jaan Raik, Sergei Devadze, 2007, 12th IEEE European Test Symposium (ETS'07).

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Yong Zhao, Görschwin Fey, Jaan Raik, 2016, 2016 Forum on Specification and Design Languages (FDL).

Embedded instrumentation toolbox for screening marginal defects and outliers for production

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2017, 2017 IEEE AUTOTESTCON.

Fault simulation with parallel exact critical path tracing in multiple core environment

Raimund Ubar, Sergei Devadze, Maksim Gorev, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Raimund Ubar, Jaan Raik, Sergei Devadze, 2015, Microprocess. Microsystems.

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2018, 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES).

Functional self-test of high-performance pipe-lined signal processing architectures

Raimund Ubar, Jaan Raik, Sergei Devadze, 2015, Microprocess. Microsystems.

Testing beyond the SoCs in a lego style

Sergei Devadze, Artur Jutman, Anton Tsertov, 2010, 2010 East-West Design & Test Symposium (EWDTS).

IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring

Sergei Devadze, Artur Jutman, Anton Tsertov, 2018, 2018 IEEE AUTOTESTCON.

Marginal PCB assembly defect detection on DDR3/4 memory bus

Sergei Devadze, Artur Jutman, Sergei Odintsov, 2017, 2017 IEEE International Test Conference (ITC).

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance

Raimund Ubar, Jaan Raik, Sergei Devadze, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

WEB-BASED SYSTEM FOR FINITE STATE MACHINES DECOMPOSITION

Sergei Devadze, S. Devadze, 2004 .

FPGA-based Embedded Virtual Instrumentation. FPGA-sisesed virtuaalsed test- ja mõõtevahendid

Sergei Devadze, Artur Jutman, 2013 .

High-Speed Logic Level Fault Simulation

Raimund Ubar, Sergei Devadze, 2011 .

Trainer 1149: a Boundary Scan Simulation Bundle for Labs

Raimund Ubar, Sergei Devadze, Artur Jutman, 2011, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011.

Open-Source JTAG Simulator Bundle for Labs

Raimund Ubar, Sergei Devadze, Artur Jutman, 2012 .

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management

Sergei Devadze, Artur Jutman, Konstantin Shibin, 2013, IEEE Design & Test.

On coverage of timing related faults at board level

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2016, 2016 21th IEEE European Test Symposium (ETS).

Web Based Tools for Synthesis and Testing of Digital Devices

Raimund Ubar, Sergei Devadze, Margus Kruus, 2002 .

Ways for board and system test to benefit from FPGA embedded instrumentation

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2019, 2019 IEEE AUTOTESTCON.

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs

Sergei Devadze, Artur Jutman, Konstantin Shibin, 2016, 2016 17th Latin-American Test Symposium (LATS).

Turning JTAG inside out for fast extended test access

Raimund Ubar, Sergei Devadze, Artur Jutman, 2009, 2009 10th Latin American Test Workshop.

Parallel fault backtracing for calculation of fault coverage

Raimund Ubar, Jaan Raik, Sergei Devadze, 2008, 2008 Asia and South Pacific Design Automation Conference.

Digital logic simulation with compressed BDDs

Raimund Ubar, Jaan Raik, Sergei Devadze, 2011, 2011 IEEE International Conference on Computer Science and Automation Engineering.

Invited paper: System-wide fault management based on IEEE P1687 IJTAG

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

Run-time reconfigurable instruments for advanced board-level testing

Sergei Devadze, Artur Jutman, Igor Aleksejev, 2016 .

DefSim – the defective IC

Raimund Ubar, Sergei Devadze, Artur Jutman, 2007 .