W. Li

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling

W. Li, A. Vandooren, Liesbeth Witters, 2018, 2018 International Conference on IC Design & Technology (ICICDT).

Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration

F. Inoue, D. Mocuta, N. Collaert, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

F. M. Bufler, F. Inoue, R. Ritzenthaler, 2018, IEEE Transactions on Electron Devices.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

B. Parvais, A. Vandooren, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

A. Hikavyy, E. Rosseel, K. Devriendt, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

D. Mocuta, J. Mitard, F. Masuoka, 2019, 2019 Symposium on VLSI Technology.

Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab

T. Schram, K. Devriendt, I. Radu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections

A. Jourdain, A. Hikavyy, G. Mannaert, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Geert Hellings, Eddy Simoen, Niamh Waldron, 2017 .

DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM

Z. Tao, K. Devriendt, D. Mocuta, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).