X. Lu

Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

K. Wostyn, J. Geypen, H. Bender, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.