Tsann-Bim Chiou

发表

Impacts of overlay correction model and metrology sampling scheme on device yield

Chui-Fu Chiu, Chun-Yen Huang, Jason Shieh, 2012, Advanced Lithography.

New overlay pattern design for real-time focus and tilt monitor

Tsann-Bim Chiou, Tan Fu Lei, Chin-Yu Ku, 2000, SPIE Advanced Lithography.

Improvement of lithography process by using a FlexRay illuminator for memory applications

Tsann-Bim Chiou, Chiang-Lin Shih, Alek Chen, 2011, Advanced Lithography.

Using intrafield high-order correction to achieve overlay requirement beyond sub-40nm node

Tsann-Bim Chiou, Alek C. Chen, Juno Lee, 2009, Advanced Lithography.

Real-time process control to prevent CD variation induced by postexposure delay

Tsann-Bim Chiou, Tan Fu Lei, Chin-Yu Ku, 2000, SPIE Advanced Lithography.

Evaluation of fine pattern definition with electron-beam direct writing lithography

Tsann-Bim Chiou, Tiao-Yuan Huang, Simon M. Sze, 2000, Advanced Lithography.

How to obtain accurate resist simulations in very low-k1 era

Tsann-Bim Chiou, Alek C. Chen, Donggyu Yim, 2006, SPIE Advanced Lithography.

Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

Tsann-Bim Chiou, Anita Fumar-Pici, Chris A. Mack, 2002, SPIE Advanced Lithography.

Double dipole lithography for 65-nm node and beyond: a technology readiness review

Tsann-Bim Chiou, Jo Finders, Eric Hendrickx, 2004, Photomask Japan.

Litho scenario solutions for FinFET SRAM 22nm node

Tsann-Bim Chiou, Alek C. Chen, Jo Finders, 2009, Lithography Asia.

The impact of lower light source bandwidth on sub-10nm process node features

Stephen Hsu, Jason Shieh, Tsann-Bim Chiou, 2017, Advanced Lithography.

Full-chip pitch/pattern splitting for lithography and spacer double patterning technologies

Tsann-Bim Chiou, Alek C. Chen, Robert John Socha, 2008, Lithography Asia.

Development of automatic OPC treatment and layout decomposition for double dipole lithography for low-k1 imaging

Stephen Hsu, Tsann-Bim Chiou, Alek C. Chen, 2005, SPIE/COS Photonics Asia.

Lithographic challenges and their solutions for critical layers in sub-14nm node logic devices

Tsann-Bim Chiou, Alek C. Chen, Mircea Dusa, 2013, Advanced Lithography.

Development of layout split algorithms and printability evaluation for double patterning technology

Tsann-Bim Chiou, Alek C. Chen, Anton van Oosten, 2008, SPIE Advanced Lithography.

65-nm full-chip implementation using double dipole lithography

Will Conley, Tsann-Bim Chiou, Jo Finders, 2003, SPIE Advanced Lithography.

Experimental verification of a model-based decomposition method for double dipole lithography

Geert Vandenberghe, Tsann-Bim Chiou, Alek Chen, 2004, SPIE Advanced Lithography.

EUV mask manufacturing readiness in the merchant mask industry

Tsann-Bim Chiou, Michael Green, Henry Kamberian, 2017, Photomask Technology.

Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers

Tsann-Bim Chiou, Alek C. Chen, Mircea Dusa, 2016, SPIE Advanced Lithography.

Simulation investigation of enabling technologies for EUV single exposure of Via patterns in 3nm logic technology

Tsann-Bim Chiou, Moyra K. McManus, Weimin Gao, 2020, Advanced Lithography.

New methods to calibrate simulation parameters for chemically amplified resists

Tsann-Bim Chiou, Anita Fumar-Pici, Doris Kang, 2002, SPIE Advanced Lithography.

Optimization of alignment/overlay sampling and marker layout to improve overlay performance for double patterning technology

Chun-Yen Huang, Tsann-Bim Chiou, Chiang-Lin Shih, 2009, Lithography Asia.

EPE variability comparison study of multiple patterning options for restricted 2D structures in advanced logic nodes

Tsann-Bim Chiou, Fung Suong Ou, Arup Saha, 2021, Advanced Lithography.

Postexposure Delay Effect on Linewidth Variation in Base Added Chemically Amplified Resist

Tsann-Bim Chiou, Tan Fu Lei, Chin-Yu Ku, 2000 .