Changsik Yoo

A common-gate switched, 0.9 W class-E power amplifier with 41% PAE in 0.25 /spl mu/m CMOS

Changsik Yoo, Qinting Huang, 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

Wonchan Kim, Changsik Yoo, Inyeol Lee, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18- ${\rm \mu}\hbox{m}$ CMOS Technology

Changsik Yoo, Young-Suk Seo, Jang-Woo Lee, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.