Paniz Foroutan

A heuristic path selection method for small delay defects test

Mehdi Kamal, Zainalabedin Navabi, Paniz Foroutan, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A mathematical model for estimating acceptable ratio of test patterns

M. H. Haghbayan, Behjat Forouzandeh, Paniz Foroutan, 2014, Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014).

An improved scheme for pre-computed patterns in core-based SoC architecture

Mahmood Fathy, Zainalabedin Navabi, Paniz Foroutan, 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

Fluorescent Imaging and Multifusion Segmentation for Enhanced Visualization and Delineation of Glioblastomas Margins

Yi Wang, George C. Giakos, Michalis Zervakis, 2021, Signals.