Yana Esteves Krasteva

Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.

Yana Esteves Krasteva, Y. Krasteva, 2011 .

Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems

Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs

Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva, 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

Partial Reconfiguration for Core Reallocation and Flexible Communications

Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva, 2006, ReCoSoC.

Generic Systolic Array for Run-Time Scalable Cores

Eduardo de la Torre, Teresa Riesgo, Andrés Otero, 2010, ARC.

Reconfigurable Networks on Chip: DRNoC architecture

Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva, 2010, J. Syst. Archit..

Flexible Core Reallocation for Virtex II Structures

Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva, 2005, ERSA.

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Eduardo de la Torre, Teresa Riesgo, Andrés Otero, 2010, 2010 International Conference on Field Programmable Logic and Applications.

A Fast Emulation-Based NoC Prototyping Framework

Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva, 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.