N Singh

Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

Zhixian Chen, Sungjoo Lee, K Banerjee, 2011, IEEE Electron Device Letters.

Multibit Programmable Flash Memory Realized on Vertical Si Nanowire Channel

N. Singh, G. Lo, D. Kwong, 2010, IEEE Electron Device Letters.

Effect of Interface Traps and Oxide Charge on Drain Current Degradation in Tunneling Field-Effect Transistors

Ming-Fu Li, N. Singh, G. Lo, 2010, IEEE Electron Device Letters.

Germanium Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated by Complementary-Metal–Oxide–Semiconductor-Compatible Process

N. Singh, G. Lo, M. Bosman, 2011, IEEE Transactions on Electron Devices.

Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With Improved Performance and Reduced Process Complexity

K. Leong, N. Singh, G. Lo, 2011, IEEE Transactions on Electron Devices.

Chip-Level Thermoelectric Power Generators Based on High-Density Silicon Nanowire Array Prepared With Top-Down CMOS Technology

K. Buddharaju, N. Singh, G. Lo, 2011, IEEE Electron Device Letters.