Gregory Fredeman

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

Erik Nelson, Toshiaki Kirihata, David Dick, 2009, IEEE Journal of Solid-State Circuits.

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

Richard E. Matick, Subramanian S. Iyer, Paul C. Parries, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

IBM z15: Physical design improvements to significantly increase content in the same technology

Ofer Geva, Sean M. Carey, Adam Jatkowski, 2020, IBM J. Res. Dev..

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Subramanian S. Iyer, Toshiaki Kirihata, Donald W. Plass, 2016, IEEE Journal of Solid-State Circuits.

4.1 22nm Next-generation IBM System z microprocessor

Matthew M. Ziegler, Jeffrey A. Zitz, Pak-kin Mak, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

2.7 IBM z15: A 12-Core 5.2GHz Microprocessor

Alper Buyuktosunoglu, Ofer Geva, Adam Jatkowski, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache

Erik Nelson, Donald W. Plass, Gregory Fredeman, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

Richard E. Matick, Subramanian S. Iyer, Paul C. Parries, 2008, IEEE Journal of Solid-State Circuits.

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

Erik Nelson, Toshiaki Kirihata, Donald W. Plass, 2011, IEEE Journal of Solid-State Circuits.