H. Brut

发表

A New Combined Methodology for Write-Margin Extraction of Advanced SRAM

N. Planes, N. Gierczynski, B. Borot, 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

Test chip characterization of X architecture diagonal lines for SoC design

S. Shah, H. Brut, J.P. Schoellkopf, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

New Method for the Extraction of the Gate Voltage Dependence of the Series Resistance in CMOS Transistors

G. Ghibaudo, H. Brut, A. Juge, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

Contribution to the characterization of the hump effect in MOSFET submicronic technologies

R.M.D.A. Velghe, H. Brut, 1999, ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307).

Low cost 65nm CMOS platform for Low Power & General Purpose applications

M. Woo, N. Planes, R. Palla, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below

D. Roy, G. Ghibaudo, A. Cros, 2008, IEEE Transactions on Semiconductor Manufacturing.

Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 /spl mu/m CMOS technology

R. Difrenza, Gerard Ghibaudo, H. Brut, 2001, ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153).

New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs

D. Fleury, H. Brut, G. Ghibaudo, 2008, 2008 IEEE International Conference on Microelectronic Test Structures.

Accuracy improvement of the "Single Pattern Driver" method for the characterization of interconnect capacitance in the context of nanometer technology development

H. Brut, B. Froment, S. Martin, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell

O. Faynot, V. Arnal, A. Vandooren, 2007, 2007 IEEE International Electron Devices Meeting.

New Mechanism of Body Charging in Partially Depleted SOI-MOSFETs with Ultra-thin Gate Oxides

S. Cristoloveanu, J. Pretet, H. Brut, 2002, 32nd European Solid-State Device Research Conference.

A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

J. Farkas, N. Planes, N. Revil, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Highly performant double gate MOSFET realized with SON process

D. Delille, T. Skotnicki, S. Monfray, 2003, IEEE International Electron Devices Meeting 2003.

New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors

Gerard Ghibaudo, Andre Juge, H. Brut, 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform

N. Planes, N. Revil, B. Tavel, 2003, IEEE International Electron Devices Meeting 2003.

New extraction method for gate bias dependent series resistance in nanometric double gate transistors

G. Ghibaudo, A. Cros, H. Brut, 2005, Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..

Physical model of threshold voltage in silicon MOS transistors including reverse short channel effect

Gerard Ghibaudo, H. Brut, A. Juge, 1995 .

Gate stack optimization for 65 nm CMOS low power and high performance platform

R. Palla, B. Tavel, C. Ortolland, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..