J.W. Lee

Highly manufacturable sub-100 nm DRAM integrated with full functionality

J.K. Cho, J.J. Lee, S. Choi, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Highly manufacturable 90 nm DRAM technology

S.H. Hong, C.H. Cho, D.J. Lee, 2002, Digest. International Electron Devices Meeting,.

A strategy for long data retention time of 512 Mb DRAM with 0.12 /spl mu/m design rule

S.H. Hong, Kinam Kim, G.T. Jeong, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Fully Integrated 56 nm DRAM Technology for 1 Gb DRAM

S.Y. Kim, W.S. Yang, D.J. Lee, 2007, 2007 IEEE Symposium on VLSI Technology.

The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs

S.G. Park, H.-J. Cho, T.S. Jeon, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Improvement of data retention time in DRAM using recessed channel array transistors with asymmetric channel doping for 80 nm feature size and beyond

Y.J. Park, J.Y. Kim, C.H. Cho, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).