G.H. Choi

Highly manufacturable sub-100 nm DRAM integrated with full functionality

J.K. Cho, J.J. Lee, S. Choi, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

A Highly Reliable Cu Interconnect Technology for Memory Device

U.I. Chung, G.H. Choi, H. Park, 2007, 2007 IEEE International Interconnect Technology Conferencee.