J. di Sarro

Investigation of SOI SCR triggering and current sustaining under DC and TLP conditions

Robert Gauthier, James Di Sarro, Junjun Li, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Effect of embedded-SiGe (eSiGe) on ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers (DTSCRs)

R. Gauthier, Rahul Mishra, Junjun Li, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

R. Gauthier, K. Chatty, E. Rosenbaum, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

Souvick Mitra, Yang Yang, Dimitris E. Ioannou, 2010, 2010 IEEE International Reliability Physics Symposium.

ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

Souvick Mitra, Robert Gauthier, Elyse Rosenbaum, 2009, 2009 31st EOS/ESD Symposium.

A dual-base triggered SCR with very low leakage current and adjustable trigger voltage

E. Rosenbaum, P. Hopper, V. Vashchenko, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Influence of Package Trace Properties on CDM Stress

Robert Gauthier, Bill Reynolds, James P. Di Sarro, 2014, IEEE Transactions on Device and Materials Reliability.