R. Steiner

An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

D. Caimi, L. Czornomaz, J. Fompeyrine, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Package optimization of a stacked die flip chip based test package

K. Pressel, C. Lee, G. Ofner, 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

Drop test reliability improvement of lead-free fine pitch BGA using different solder ball composition

C. Birzer, C. Birzer, R. Steiner, 2005, 2005 7th Electronic Packaging Technology Conference.