Jae-kyu Lee

High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's

Jai-Hoon Sim, Kinam Kim, Jae-Kyu Lee, 1999 .

The impact of isolation pitch scaling on V/sub TH/ fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetration

Jai-Hoon Sim, Kinam Kim, Jae-Kyu Lee, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

Novel Cell Architecture for High Performance of 512-Mb DRAM with 0.12-µm Design Rule

Kinam Kim, Ju-Yong Lee, Min-Sang Kim, 2002 .