M. Hioki

发表

Measurement of Vth variation due to STI stress and inverse narrow channel effect at ultra-low voltage in a variability-suppressed process

T. Sekigawa, Y. Ogasahara, T. Nakagawa, 2015, Proceedings of the 2015 International Conference on Microelectronic Test Structures.

Compact model for ultra-short channel four-terminal DG MOSFETs for exploring circuit characteristics

Masakazu Hioki, Tadashi Nakagawa, Eiichi Suzuki, 2005 .

Capacitance Model for Four-Terminal DG MOSFETs

S. O'Uchi, T. Sekigawa, T. Nakagawa, 2006 .

Improved Compact Model for Four-Terminal DG MOSFETs

E. Suzuki, T. Sekigawa, T. Nakagawa, 2004 .

More than an order of magnitude energy improvement of FPGA by combining 0.4V operation and Multi-Vt optimization of 20k body bias domains

Yasuhiro Ogasahara, Chao Ma, Toshiyuki Tsutsumi, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

Hanpei Koike, Masakazu Hioki, H. Koike, 2016, IEICE Trans. Inf. Syst..

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Yasuhiro Ogasahara, Chao Ma, Toshiyuki Tsutsumi, 2014 .

Fully-functional FPGA prototype with fine-grain programmable body biasing

Hanpei Koike, Toshiyuki Tsutsumi, Masakazu Hioki, 2013, FPGA '13.

Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA

Hanpei Koike, Toshiyuki Tsutsumi, Masakazu Hioki, 2007, IEICE Trans. Inf. Syst..

Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components

Hanpei Koike, Toshiyuki Tsutsumi, Masakazu Hioki, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Evaluation of granularity on threshold voltage control in flex power FPGA

Hanpei Koike, Toshiyuki Tsutsumi, Masakazu Hioki, 2006, 2006 IEEE International Conference on Field Programmable Technology.

A spiking neuron implemented in VLSI

M. Rozenberg, O. Schneegans, P. Stoliar, 2022, Journal of Physics Communications.

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

Hanpei Koike, Toshiyuki Tsutsumi, Masakazu Hioki, 2007, FPGA '07.

An analysis of program and erase operation for FC-SGT flash memory cells

Tetsuo Endoh, Fujio Masuoka, Masakazu Hioki, 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

Proposal of Analytical Method of Lower Diffusion Layer for Three Dimensional Structured Surrounding Gate Transistor (SGT)

Tetsuo Endoh, Fujio Masuoka, Hiroshi Sakuraba, 2003 .

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

Hanpei Koike, Toshiyuki Tsutsumi, Masakazu Hioki, 2008, TRETS.