Akira Nagoya

Kouichi Nagami, Tsunemichi Shiozawa, Akira Nagoya, 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

Solving satisfiability problems using reconfigurable computing : Reconfigurable and Adaptive VLSI Systems

Makoto Yokoo, Hiroshi Sawada, Takayuki Suyama, 2001 .

Multi-Level Optimization for Large Scale ASICS.

Kiyoshi Oguri, Akira Nagoya, Ryo Nomura, 1990, ICCAD 1990.

Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture

Hideyuki Ito, Norbert Imlig, Kouichi Nagami, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

Summation algorithms on constrained reconfigurable meshes

Akihiro Matsuura, Akira Nagoya, 1999, Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99).

Restructuring logic representations with easily detectable simple disjunctive decompositions

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 1998, Proceedings Design, Automation and Test in Europe.

An Efficient Method for Finding an Optimal Bi-Decomposition (Special Section on VLSI Design and CAD Algorithms)

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 1998 .

Synthesis From Pure Behavioral Descriptions

Kiyoshi Oguri, Akira Nagoya, Yukihiro Nakamura, 1991 .

Multi-level logic optimization for large scale ASICs

Kiyoshi Oguri, Yukihiro Nakamura, Akira Nagoya, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology

Hiroshi Sawada, Kazuo Aoyama, Kazuo Nakajima, 2000, FPL.

A Method for Improving Combinational Circuits using Simple Disjunctive Decompositions

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 1998 .

A General Framework to Use Various Decomposition Methods for LUT Network Synthesis

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 2001 .

A study on the circuit implementation of an asynchronous LSI with a self-reconfiguration feature

Hideyuki Ito, Hiroshi Nakada, Ryusuke Konishi, 2002 .

Implementation of Scalable Communication Switches on PCA

Yuichi Okuyama, Tsunemichi Shiozawa, Hideyuki Tsuboi, 2002 .

A new method to express functional permissibilities for LUT based FPGAs and its applications

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 1996, Proceedings of International Conference on Computer Aided Design.

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

Hiroshi Sawada, Takayuki Suyama, Akira Nagoya, 1995, ICCAD.

Self-referable, Self-reorganisable, and Self-reproducible Hardware with Plastic Cell Architecture

Hideyuki Ito, Hiroshi Nakada, Ryusuke Konishi, 2002 .

Dynamically Reconfigurable Logic LSI designed as Fully Asynchronous System - PCA-2

Akira Nagoya, 2003 .

Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations

Akihiro Matsuura, Akira Nagoya, 1998 .

An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 2000, Proceedings - Design Automation Conference.

Solving satisfiability problems by using reconfigurable hardware

Makoto Yokoo, Hiroshi Sawada, Takayuki Suyama, 2003 .

Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA

Yuichiro Shibata, Kiyoshi Oguri, Akira Nagoya, 2003, Asia-Pacific Computer Systems Architecture Conference.

Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation

Makoto Yokoo, Takayuki Suyama, Akira Nagoya, 1999, CP.

An integrated approach for synthesizing LUT networks

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture

Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya, 1999, IPPS/SPDP Workshops.

DIPS-11/5E series mainframes

Akira Nagoya, Y. Obashi, S. Shiokawa, 1987 .

Dynamically reconfigurable logic LSI-PCA-1

Hideyuki Ito, Hiroshi Nakada, Yuichi Okuyama, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

High-Level Synthesis Design at NTT Systems Labs (Special Issue on Synthesis and Verification of Hardware Design)

Kiyoshi Oguri, Yukihiro Nakamura, Akira Nagoya, 1993 .

Asynchronous Dynamically Reconfigurable Logic LSIs Suitable for Technology Scaling

Akira Nagoya, 2004 .

A New Method to Express Functional Permissibilities and Its Application to FPGA Synthesis

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 1997 .

Soft decision maximum likelihood decoders for binary linear block codes implemented on FPGAs (abstract)

Hidehisa Nagano, Takayuki Suyama, Akira Nagoya, 1998, FPGA '98.

Acceleration of linear block code evaluations using new reconfigurable computing approach

Hidehisa Nagano, Takayuki Suyama, Akira Nagoya, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Logic synthesis and optimization methods for Sea-of-LUTs based PCA

Hiroshi Sawada, Minoru Inamori, Shigeru Yamashita, 2000 .

Restricted simple disjunctive decompositions based on grouping symmetric variables

Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya, 1997, Proceedings Great Lakes Symposium on VLSI.

Acceleration of Analysis Processing on Decentralized Performance Profiling System Using Virtual Machines

Masao Yamamoto, Kohta Nakashima, Toshihiro Yamauchi, 2018, 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW).

An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture

Kiyoshi Oguri, Hiroshi Nakada, Norbert Imlig, 2000, FPL.

Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic

Makoto Yokoo, Takayuki Suyama, Akira Nagoya, 1999, IPPS/SPDP Workshops.

PCA-1: a fully asynchronous, self-reconfigurable LSI

Kiyoshi Oguri, Hideyuki Ito, Hiroshi Nakada, 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

Network Processor for High-Speed Network and Quick Programming

Toshiaki Miyazaki, Hiroyuki Ochi, Takahiro Murooka, 2007, J. Circuits Syst. Comput..

A hardware/software codesign method for a general purpose reconfigurable co-processor

Akira Nagoya, M. Yukishita, S. Kimura, 1997, Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97.

Restructuring Logic Representations with Simple Disjunctive Decompositions (Special Section on VLSI Design and CAD Algorithms)

Shigeru Yamashita, Akira Nagoya, Hiroshi Sawada, 1998 .

Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications

Shigeru Yamashita, Akira Nagoya, Hiroshi Sawada, 2000 .