Anees Ullah

发表

Multiple Cell Upset Injection in BRAMs for Xilinx FPGAs

Pedro Reviriego, Juan Antonio Maestro, Alfonso Sánchez-Macián, 2018, IEEE Transactions on Device and Materials Reliability.

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Ernesto Sánchez, Luca Sterpone, Anees Ullah, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

Ernesto Sánchez, Luca Sterpone, Carles Ferrer, 2017, Microelectron. Reliab..

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems

Matteo Sonza Reorda, Luca Sterpone, Anees Ullah, 2017, IEEE Transactions on Computers.

Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs

Pedro Reviriego, Juan Antonio Maestro, Alexis Ramos, 2018, IEEE Transactions on Computers.

On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs

Luca Sterpone, Anees Ullah, 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs

Pedro Reviriego, Zhan Xu, Zhen Gao, 2019, IEEE Transactions on Nanotechnology.

A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs

Luca Sterpone, Carles Ferrer, Anees Ullah, 2017, J. Syst. Archit..

Low delay Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes

Pedro Reviriego, Liyi Xiao, Jiaqiang Li, 2019 .

Error Detection and Correction in SRAM Emulated TCAMs

Salvatore Pontarelli, Pedro Reviriego, Anees Ullah, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Comparison Based Analysis of Different Cryptographic and Encryption Techniques Using Message Authentication Code (MAC) in Wireless Sensor Networks (WSN) pdf

Muhammad Bilal, Sadaqat ur Rehman, Obaid ur Rehman, 2012, ArXiv.

Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays

Giuseppe Bianchi, Salvatore Pontarelli, Pedro Reviriego, 2018, 2018 IEEE 19th International Conference on High Performance Switching and Routing (HPSR).

BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs

Waleed Ahmad, Pedro Reviriego, Anees Ullah, 2020 .

An Efficient Methodology for On-Chip SEU Injection in Flip-Flops for Xilinx FPGAs

Pedro Reviriego, Juan Antonio Maestro, Anees Ullah, 2018, IEEE Transactions on Nuclear Science.

PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration

Salvatore Pontarelli, Pedro Reviriego, Anees Ullah, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Majority Voting-Based Reduced Precision Redundancy Adders

Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro, 2018, IEEE Transactions on Device and Materials Reliability.

Isolation Design Flow Effectiveness Evaluation Methodology for Zynq SoCs

Pedro Reviriego, Affaq Qamar, Anees Ullah, 2020 .

Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs

Luca Sterpone, Anees Ullah, 2014, J. Electron. Test..

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture

Luca Sterpone, Davide Sabena, Mario Porrmann, 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Pedro Reviriego, Anees Ullah, Ali Zahir, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Intelligent Energy-Based Modified Super Twisting Algorithm and Factional Order PID Control for Performance Improvement of PMSG Dedicated to Tidal Power System

Anees Ullah, Zaheer Farooq, Nasim Ullah, 2021, IEEE Access.

Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations

Pedro Reviriego, Anees Ullah, Zhen Gao, 2022, IEEE Transactions on Emerging Topics in Computing.

Switch-Based High Cardinality Node Detection

Pedro Reviriego, Malik Najmus Siraj, Anees Ullah, 2021, IEEE Embedded Systems Letters.

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Pedro Reviriego, Fahad Bin Muslim, Anees Ullah, 2021 .

Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs

Pedro Reviriego, Anees Ullah, Syed Riaz Ul Hassnain, 2021, IEEE Embedded Systems Letters.