Howard Cam Luong

25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter

Zhihua Wang, Baoyong Chi, Zhiqiang Huang, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A Reconfigurable CMOS Power Amplifier Using Adaptive Biasing Technique for Wireless Monitoring Applications

Chung-Ching Lin, Nahid Mirzaie, Ahmed Alzahmi, 2019 .

20.3 An 86-to-94.3GHz transmitter with 15.3dBm output power and 9.6% efficiency in 65nm CMOS

Lianming Li, Yue Chao, Howard Cam Luong, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A dithering-less 54.79-to-63.16GHz DCO with 4-Hz frequency resolution using an exponentially-scaling C-2C switched-capacitor ladder

Zhiqiang Huang, Howard Cam Luong, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

An energy harvesting circuit for GHz on-chip antenna measurement

Howard Cam Luong, Huyen Le, Neric Fong, 2011, 2011 IEEE International Symposium on Radio-Frequency Integration Technology.

RF energy harvesting circuit with on-chip antenna for biomedical applications

Howard Cam Luong, Huyen Le, Neric Fong, 2010, International Conference on Communications and Electronics 2010.

An 82-to-108GHz −181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDC

Zhiqiang Huang, Howard Cam Luong, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL

Zhiqiang Huang, Lianming Li, Howard Cam Luong, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).