F. Huang

PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

M. Mendicino, D. Jovanovic, O. Adetutu, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A high performance 1.5 V, 0.10 /spl mu/m gate length CMOS technology with scaled copper metallization

S. Veeraraghavan, M. Kling, C. Feng, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A high density 0.10 /spl mu/m CMOS technology using low K dielectric and copper interconnect

D. Reber, G. Yeap, M. Aminpur, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Optimizing ALD WN Process for 65nm Node CMOS Contact Application

Y.-L. Chang, S.F. Tzou, F. Huang, 2007, 2007 IEEE International Interconnect Technology Conferencee.