M. Nakamura

A 255 Mb SDRAM with subthreshold leakage current suppression

S. Miyatake, Y. Nakagome, K. Kajigaya, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A 29 ns 64 Mb DRAM with hierarchical array architecture

T. Takahashi, M. Morino, K. Komatsuzaki, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.