Hong-Wun Gao

A Quasi-3-D Scaling Length Model for Trapezoidal FinFET and Its Application to Subthreshold Behavior Analysis

Yeong-Her Wang, T. Chiang, Hong-Wun Gao, 2017, IEEE Transactions on Nanotechnology.

A unified quantum scaling length model for nanometer multiple-gate MOSFETs

Yeong-Her Wang, T. Chiang, Hong-Wun Gao, 2018, 2018 7th International Symposium on Next Generation Electronics (ISNE).

A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates

Yeong-Her Wang, T. Chiang, Hong-Wun Gao, 2018, IEEE Transactions on Nanotechnology.

A new interface-trapped-charge-degraded subthreshold current model for cylindrical, surrounding-gate (CSRG) MOSFETs

T. Chiang, Hong-Wun Gao, Y. Chiu, 2014, 2014 International Symposium on Next-Generation Electronics (ISNE).