E. Yamamoto

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

Yoshihito Amemiya, Shinsuke Konaka, E. Yamamoto, 1989 .

Wafer Handling and Thinning Processes

Toshihiro Ito, E. Yamamoto, T. Haimoto, 2015 .

Development of Cu-less TSV reveal process using Si/Cu grinding, electroless Ni plating, and alkaline etching of Si

Masahiro Aoyagi, Naoya Watanabe, Eiichi Yamamoto, 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).

Metal contamination evaluation of a TSV reveal process using direct Si/Cu grinding and residual metal removal

N. Watanabe, M. Aoyagi, E. Yamamoto, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Evaluation of a copper metallization process and the electrical characteristics of copper-interconne

M. Miyake, Y. Okazaki, H. Inokawa, 1996 .

Investigation of metal contamination induced by a through silicon via reveal process using direct Si/Cu grinding and residual metal removal

N. Watanabe, M. Aoyagi, E. Yamamoto, 2016 .

Planarized multilevel interconnection using chemical mechanical polishing of selective CVD-Al via plugs

T. Amazawa, Y. Arita, E. Yamamoto, 1998 .

A low-permittivity interconnection using an SiBN interlayer

Shinsuke Konaka, T. Makino, S. Konaka, 1989 .

Improvement of a TSV Reveal Process Comprising Direct Si/Cu Grinding and Residual Metal Removal

N. Watanabe, M. Aoyagi, E. Yamamoto, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Preparation of Low-Reflectivity Amorphous Silicon Using DC Magnetron Sputtering

Takahiro Makino, T. Makino, Kazuyoshi Kamoshida, 1984 .