S. Burns

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

10nm FINFET technology for low power and high performance applications

D. Chanemougame, P. Oldiges, B. Haran, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

M. Raymond, M. Burkhardt, S. Paparao, 2008, 2008 IEEE International Electron Devices Meeting.

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

T. Spooner, M. Tagami, M. Colburn, 2011, 2011 IEEE International Interconnect Technology Conference.