Ahmer Syed

发表

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

Robert Darveaux, Jim Heckman, Ahmer Syed, 2000 .

Interconnect reliability prediction for wafer level packages (WLP) for temperature cycle and drop load conditions

Ahmer Syed, Tong Cui, Beth Keser, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

BOARD DESIGN, SURFACE MOUNT ASSEMBLY AND BOARD LEVEL RELIABILITY ASPECTS OF FUSIONQUAD TM PACKAGES

Ahmer Syed, Sundar Sethuraman, WonJoon Kang, 2008 .

Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's

Riko Radojcic, Mark Nakamoto, Wei Lin, 2012 .

Issues in fatigue life prediction model for underfilled flip chip bump

Nokibul Islam, Ahmer Syed, WonJoon Kang, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Packaging Challenges for the Next Generation of Mobile Devices

Ahmer Syed, 2017 .

Are we over designing for solder joint reliability? Field vs. accelerated conditions, realistic vs. specified requirements

Ahmer Syed, M. Doty, 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).

Design for board trace reliability of WLCSP under drop test

Ahmer Syed, Hun Shen Ng, Tong Yan Tee, 2009, EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.

Module/SiP Packaging Trends

Ryan Lane, Ahmer Syed, Piyush Gupta, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Multi DOE Study on 28nm (RF) WLP Package to Investigate BLR Performance of Large WLP Die with 0.35mm Ball Pitch Array

Steven X. Xu, Ahmer Syed, Tong Cui, 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

Package design and material impact on board level reliability of fine pitch packages

Ahmer Syed, 2009, 2009 IEEE International Reliability Physics Symposium.

A Methodology for Chip - Package Interaction (CPI) Modeling in 3D IC Structures

Riko Radojcic, Mark Nakamoto, Wei Lin, 2012 .

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

Riko Radojcic, Brian Henderson, Ahmer Syed, 2017 .

Quantifying impact of design parameters on Ultra-Low k ILD reliability in fine pitch Cu bump interconnect structures

Ahmer Syed, Lily Zhao, Tong Cui, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

The International Magazine for Device and Wafer-level Test, Assembly, and Packaging Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS, MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century.

Kang Chen, James McLeish, Randy Schueller, 2014 .

Advances in WLCSP Technologies to Enable Cost-Reduction

Ahmer Syed, Boyd Rogers, Rex Anderson, 2010 .

Limitations of Norris-Landzberg equation and application of damage accumulation based methodology for estimating acceleration factors for Pb free solders

Ahmer Syed, A. Syed, 2010, 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE).

Electromigration reliability and current carrying capacity of various WLCSP interconnect structures

Ahmer Syed, Karthikeyan Dhandapani, Robert Moody, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Factors affecting electromigration and current carrying capacity of FC and 3D IC interconnects

Ahmer Syed, A. Syed, 2010, 2010 12th Electronics Packaging Technology Conference.

Relative and absolute warpage modeling on molded packages

Ahmer Syed, Jiantao Zheng, Manuel Aldrete, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).