M. Fujiwara

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, 2005 IEEE International SOI Conference Proceedings.

Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Y. Toyoshima, K. Ohuchi, N. Aoki, 2006, 2006 International Electron Devices Meeting.

Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

N. Nagashima, K. Ohuchi, H. Ishiuchi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

3D Semicircular Flash Memory Cell: Novel Split-Gate Technology to Boost Bit Density

M. Kondo, T. Ogura, F. Arai, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

New optimization guidelines for sub-0.1 /spl mu/m CMOS technologies with 2 nm NO gate oxynitrides

Y. Toyoshima, M. Takayanagi, M. Fujiwara, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides

T. Ohguro, Y. Toyoshima, M. Takayanagi, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).