A. Hasegawa

Effect of wafer bias frequency on microtrenching during high selective gate etching

H. Morioka, T. Ishida, N. Abe, 1999, 1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395).

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.