Rie Soejima

A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis

Yuichiro Shibata, Kiyoshi Oguri, Keisuke Dohi, 2014, CARN.

Comparative Evaluation of FPGA Implementation Alternatives for Real-Time Robust Ellipse Estimation based on RANSAC Algorithm

Yuichiro Shibata, Kiyoshi Oguri, Theint Theint Thu, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization

Yuichiro Shibata, Kiyoshi Oguri, Rie Soejima, 2016, CARN.

Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration

Yuichiro Shibata, Kiyoshi Oguri, Keisuke Dohi, 2015, IEICE Trans. Inf. Syst..

HLS-Based FPGA Acceleration of Building-Cube Stencil Computation

Yuichiro Shibata, Kiyoshi Oguri, Rie Soejima, 2017, CISIS.

Discussion on power performance optimization for stream processing on an FPGA accelerator

Yuichiro Shibata, Kiyoshi Oguri, Rie Soejima, 2015 .