V. McNeil

Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 /spl mu/m CMOS process

A. Amerasekera, M. Rodder, A. Amerasekera, 1996, International Electron Devices Meeting. Technical Digest.

An efficient method for modeling the effect of implant damage on NMOS devices using effective profiles and device simulation

S. Saxena, K. Vasanth, S. List, 1996, International Electron Devices Meeting. Technical Digest.