Stanley Schuster

Tradeoffs in power-efficient issue queue design

Pradip Bose, David H. Albonesi, Alper Buyuktosunoglu, 2002, ISLPED '02.

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

Richard E. Matick, Subramanian S. Iyer, Paul C. Parries, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A circuit level implementation of an adaptive issue queue for power-aware microprocessors

David M. Brooks, Pradip Bose, David H. Albonesi, 2001, GLSVLSI '01.

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor

James E. Smith, Michael Gschwind, Tejas Karkhanis, 2002, PACS.

Logic-based eDRAM: Origins and rationale for use

Richard E. Matick, Stanley Schuster, S. Schuster, 2005, IBM J. Res. Dev..

Design and characteristics of n-channel insulated-gate field-effect transistors

Robert H. Dennard, Stanley Schuster, Dale L. Critchlow, 2000, IBM J. Res. Dev..

Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors

Manish Gupta, David M. Brooks, Pradip Bose, 2000, IEEE Micro.

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

Richard E. Matick, Subramanian S. Iyer, Paul C. Parries, 2008, IEEE Journal of Solid-State Circuits.

An Adaptive Issue Queue for Reduced Power at High Performance

David M. Brooks, Pradip Bose, David H. Albonesi, 2000, PACS.

Synchronous interlocked pipelines

Pradip Bose, Prabhakar Kudva, Peter W. Cook, 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

Dynamically Tuning Processor Resources with Adaptive Processing

Michael C. Huang, Pradip Bose, Eby G. Friedman, 2003, Computer.