P.K. Meher

High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2m)

P.K. Meher, P. Meher, 2007, 2007 6th International Conference on Information, Communications & Signal Processing.

Novel Recursive Solution for Area-Time Efficient Systolization of Discrete Fourier Transform

P.K. Meher, J.C. Patra, A.P. Vinod, 2007, 2007 International Symposium on Signals, Circuits and Systems.

Systolic Architecture for Transposition-Free VLSI Implementation of Separable 2-D DWT

P.K. Meher, B.K. Mohanty, 2006, 2006 10th IEEE Singapore International Conference on Communication Systems.

A new convolutional formulation of discrete cosine transform for systolic implementation

P.K. Meher, J.C. Patra, 2007, 2007 6th International Conference on Information, Communications & Signal Processing.