Siyoung Choi

A stacked memory device on logic 3D technology for ultra-high-density data storage

Sung Min Kim, Joo-Tae Moon, Rob N Candler, 2011, Nanotechnology.

Fin-channel-array transistor (FCAT) featuring sub-70nm low power and high performance DRAM

Joo-Tae Moon, U-In Chung, Sun-Ghil Lee, 2003, IEEE International Electron Devices Meeting 2003.

High speed and nonvolatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier

U-In Chung, Joo Tae Moon, Siyoung Choi, 2003, IEEE International Electron Devices Meeting 2003.

1D thickness scaling study of phase change material (Ge2Sb2Te5) using a pseudo 3-terminal device

H.-S. Philip Wong, Joo-Tae Moon, Yuan Zhang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Effect of pre-existing void in sub-30nm Cu interconnect reliability

Joo-Tae Moon, J. Moon, Siyoung Choi, 2010, 2010 IEEE International Reliability Physics Symposium.

Characterization of threshold voltage instability after program in charge trap flash memory

Joo-Tae Moon, Sunjung Kim, Siyoung Choi, 2009, 2009 IEEE International Reliability Physics Symposium.