Jaegoo Lee

Novel Cell Architecture for High Performance of 512-Mb DRAM with 0.12-µm Design Rule

Kinam Kim, Ju-Yong Lee, Min-Sang Kim, 2002 .

Flash Memory Scaling: From Material Selection to Performance Improvement

T. Hou, E. Kan, Jaegoo Lee, 2008 .

Ni-based self-aligned silicidation (SAS) process on source and drain for planar polysilicon TFT low-voltage flash memory cell

D. Muller, R. V. van Dover, E. Kan, 2009, 2009 Device Research Conference.

Material and electrical characterization of stackable planar polysilicon TFT flash memory cell with metal nanocrystals and high-k dielectrics

D. Muller, T. Hou, R. V. van Dover, 2008, 2008 IEEE International SOI Conference.

Planar polysilicon TFT low-voltage flash memory cell with Al2O3 tunnel dielectric and (Ti,Dy) O control dielectric for three-dimensional integration

T. Hou, R. V. van Dover, E. Kan, 2008, 2008 Device Research Conference.

Three-Dimensional Integration For Flash Memory Cell

Jaegoo Lee, Jaegoo Lee, 2009 .

Void Growth as a Function of Residual Stress Level in Thin, Narrow Aluminum Lines

M. Korhonen, Che-yu Li, P. Borgesen, 1991 .

Flash Memory Scaling: From Material Selection to Performance Improvement

T. Hou, E. Kan, Jaegoo Lee, 2008 .