Joon-Ho Sung

Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60㎚ Feature Sized DRAM

Seung-Chul Yang, Soo-Ho Shin, Tae-Young Chung, 2006 .

Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

Ju-Yong Lee, Kinam Kim, Seung-Chul Yang, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..