A. Pouydebasque

发表

3Dstacked channels: howseries resistances canlimit 3Ddevices performance

Yves Campidelli, E. Bernard, Philippe Coronel, 2007 .

Gate-All-Around technology: taking advantage of ballistic transport ?

G. Ghibaudo, G. Bidal, T. Skotnicki, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity

M. Vinet, J.-M. Hartmann, E. Augendre, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

T. Skotnicki, S. Monfray, F. Arnaud, 2008, IEEE Transactions on Electron Devices.

Refinement of the Subthreshold Slope Modeling for Advanced Bulk CMOS Devices

T. Skotnicki, A. Pouydebasque, R. Gwoziecki, 2007, IEEE Transactions on Electron Devices.

One mask architecture for 3D front-end integration

V. Arnal, D. Delille, S. Borel, 2008, 2008 9th International Conference on Ultimate Integration of Silicon.

First Demonstration of Deep Sub-Micron Germanium-on-Insulator PMOSFET with Adapted Threshold Voltage

J.-M. Hartmann, S. Deleonibus, E. Augendre, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

High-k/metal Gate GeOI pMOSFET: Validation of the Lim&Fossum model for interface trap density extraction

X. Garros, Emmanuel Augendre, M. Vinet, 2008 .

Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

P. Batude, M. Vinet, B. Giffard, 2009, IEEE Transactions on Electron Devices.

Metallic Source/Drain Architecture for Advanced MOS Technology: an overview of METAMOS results

Jean-Pierre Raskin, Elena Pascual, Emmanuel Dubois, 2009 .

3D stacked channels: how series resistances can limit 3D devices performance

F. Andrieu, T. Ernst, S. Deleonibus, 2007, 2007 IEEE International SOI Conference.

Si/SiGe Epitaxy: a Ubiquitous Process for Advanced Electronics

P. Chevalier, T. Skotnicki, S. Monfray, 2007, 2007 IEEE International Electron Devices Meeting.

20nm gate length trigate pFETs on strained SGOI for high performance CMOS

X. Garros, O. Faynot, P. Batude, 2010, 2010 Symposium on VLSI Technology.

CMOS integration of solid phase epitaxy for sub-50nm devices

T. Skotnicki, R. El-Farhane, C. Laviron, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

X. Garros, J. Mazurier, O. Faynot, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications

Stephane Monfray, Frederic Boeuf, T. Skotnicki, 2005 .

High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

T. Skotnicki, F. Leverd, D. Dutartre, 2008, IEEE Transactions on Nanotechnology.

Impact of scaling on electrostatics of Germanium-channel MOSFET — analytical study

G. Ghibaudo, T. Skotnicki, S. Monfray, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS

N. Planes, D. Delille, T. Skotnicki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

G. Le Carval, M. Vinet, S. Deleonibus, 2008 .

Process optimization and performance analysis of an electrostatically actuated varifocal liquid lens

C. Kopp, A. Pouydebasque, N. Sillon, 2011, 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference.

Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors

P. Batude, M. Vinet, Y. Cazaux, 2008, 2008 IEEE International Electron Devices Meeting.

A new step in GeOI pFET scaling and Off-State current reduction: 30nm gate length and record ION/IOFF ratio

O. Faynot, M. Vinet, D. Lafond, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate

X. Garros, G. Reimbold, Emmanuel Augendre, 2009 .

A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below

Nicolas Loubet, Romain Wacquez, M.-P. Samson, 2007 .

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

O. Faynot, M. Vinet, C. Tabone, 2010, IEEE Electron Device Letters.

Si1-xGex/Si Selective Etch with HCl for Thin Si-Channel Transistors Integration

Nicolas Loubet, Stephane Denorme, Thomas Skotnicki, 2007 .

GeOI and SOI 3D monolithic cell integrations for high density applications

X. Garros, O. Rozeau, O. Faynot, 2006, 2009 Symposium on VLSI Technology.

Impact of the lateral source/drain abruptness on MOSFET characteristics and transport properties

T. Skotnicki, A. Pouydebasque, H. Jaouen, 2003, IEEE International Electron Devices Meeting 2003.

A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels : A High Co-Integration Potential

Nicolas Loubet, Romain Wacquez, M.-P. Samson, 2006 .

High Threshold Voltage Matching Performance on Gate-All-Around MOSFET

Thomas Skotnicki, Gerard Ghibaudo, K. Rochereau, 2006 .