S.N. Storino

A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor

J.B. Kuang, T.C. Buchholtz, S.M. Dance, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

D.H. Allen, S.N. Storino, A.G. Aipperspach, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

The design and implementation of double-precision multiplier in a first-generation CELL processor

J.B. Kuang, T.C. Buchholtz, S.M. Dance, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

A 660 MHz 64b SOI processor with Cu interconnects

T.C. Buchholtz, S.N. Storino, S. Storino, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).