D. Wendel

A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor

J.B. Kuang, T.C. Buchholtz, S.M. Dance, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

O. Takahashi, D. Wendel, S.R. Cottier, 2008, IEEE Journal of Solid-State Circuits.

Level-2 cache for high performance /390 μ-processors

D. Wendel, P. Coppens, H. Barsuhn, 1992, Microprocess. Microprogramming.

The Power Conscious Synergistic Processor Element of a Cell Processor

B. Flachs, S.H. Dhong, O. Takahashi, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

The design and implementation of double-precision multiplier in a first-generation CELL processor

J.B. Kuang, T.C. Buchholtz, S.M. Dance, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

S.H. Dhong, O. Takahashi, H. Murakami, 2006, IEEE Journal of Solid-State Circuits.

A 1.8 GHz Instruction Window Buffer

J. Leenstra, D. Wendel, J. Pille, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).