Naran Sirisantana

Enhancing yield at the end of the technology roadmap

Kaushik Roy, Bipul Chandra Paul, Naran Sirisantana, 2004, IEEE Design & Test of Computers.

Integer linear programming-based synthesis of skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2003, ASP-DAC '03.

Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies

Kaushik Roy, Naran Sirisantana, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Low-power design using multiple channel lengths and oxide thicknesses

Kaushik Roy, Naran Sirisantana, 2004, IEEE Design & Test of Computers.

Synthesis of skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2005, TODE.

High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

Kaushik Roy, Liqiong Wei, Naran Sirisantana, 2000, Proceedings 2000 International Conference on Computer Design.

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2001, ISLPED '01.

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

Kaushik Roy, Dinesh Somasekhar, Naran Sirisantana, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Synthesis of selectively clocked skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2002, Proceedings International Symposium on Quality Electronic Design.

Design considerations for high-performance low -power circuits for scaled technologies

Naran Sirisantana, 2003 .