M. Hiroi

Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier

Y. Hayashi, N. Furutake, M. Ueki, 2002, Digest. International Electron Devices Meeting,.

Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film

T. Kikkawa, M. Tada, Y. Hayashi, 2008, IEEE Transactions on Semiconductor Manufacturing.

Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

T. Takeuchi, M. Tada, N. Inoue, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Dual hard mask process for low-k porous organosilica dielectric in copper dual damascene interconnect fabrication

Yoshihiro Hayashi, Munehiro Tada, Shuichi Saito, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Effects of Ti addition on via reliability in Cu dual damascene interconnects

N. Inoue, Y. Hayashi, N. Furutake, 2004, IEEE Transactions on Electron Devices.

Suppression of bimodal stress-induced voiding using high-diffusive dopant from Cu-alloy seed layer

Hidenobu Miyamoto, K. Motoyama, K. Fujii, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

Cu dual damascene interconnects in porous organosilica film with organic hard-mask and etch-stop layers for 70 nm-node ULSIs

Yoshihiro Hayashi, Munehiro Tada, Shuichi Saito, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).