T. Usui

Identification of electromigration dominant diffusion path for Cu damascene interconnects and effect of plasma treatment and barrier dielectrics on electromigration performance

H. Shibata, T. Hasegawa, H. Shibata, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Y. Toyoshima, K. Ohuchi, N. Aoki, 2006, 2006 International Electron Devices Meeting.

56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme

E. Soda, T. Spooner, J. C. Arnold, 2012, 2012 IEEE International Interconnect Technology Conference.

EM lifetime improvement of Cu damascene interconnects by p-SiC cap layer

M. Hatano, Hisashi Kaneko, Y. Shimooka, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

Significant improvement in electromigration of reflow-sputtered Al-0.5wt%Cu/Nb-liner dual damascene interconnects with low-k organic SOG dielectric

Hisashi Kaneko, Masahiko Hasunuma, Toshiaki Watanabe, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAM

H. Shibata, M. Fukasawa, T. Usui, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

T. Spooner, M. Tagami, M. Colburn, 2011, 2011 IEEE International Interconnect Technology Conference.