C. Dachs

RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications

R. Rooyackers, A. Veloso, M. Jurczak, 2002, 32nd European Solid-State Device Research Conference.

Evidence of the ion's impact position effect on SEB in N-channel power MOSFETs

J. Gasiot, G. Bruguier, J.-M. Palau, 1994 .

SEGR and SEB in n-channel power MOSFETs

Kenneth F. Galloway, J. R. Brews, Ronald D. Schrimpf, 1996 .

Simulation aided hardening of N-channel power MOSFETs to prevent single event burnout

J. Gasiot, G. Bruguier, J.-M. Palau, 1995 .

Experimental and 2D simulation study of the single-event burnout in N-channel power MOSFETs

J. Gasiot, J.-M. Palau, P. Tastet, 1993 .

A physical interpretation for the single-event-gate-rupture cross-section of n-channel power MOSFETs

Kenneth F. Galloway, Ronald D. Schrimpf, C. F. Wheatley, 1996 .

Heavy ion induced failures in a power IGBT

Robert Ecoffet, J. Gasiot, J.-M. Palau, 1997 .

Gate stack optimization for 65 nm CMOS low power and high performance platform

R. Palla, B. Tavel, C. Ortolland, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications

R. Degraeve, A. Veloso, M. Jurczak, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..