Dong-Seok Kang

A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth

Xuefan Jin, Kee-Won Kwon, Dong-Seok Kang, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 6.4–11 Gb/s Wide-Range Referenceless Single-Loop CDR With Adaptive JTOL

Hye-Ran Kim, Dong-Seok Kang, Jung-Hoon Chun, 2020, IEEE Solid-State Circuits Letters.

A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique

Hye-Ran Kim, Jahoon Jin, Dong-Seok Kang, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth

Xuefan Jin, Dong-Seok Kang, Youngjun Ko, 2020, IEEE Journal of Solid-State Circuits.