Y. Hirano

Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications

Shigenobu Maeda, Toshiaki Iwamatsu, Shigeto Maegawa, 2002, Digest. International Electron Devices Meeting,.

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2001 .

Tantalum-gate SOI MOSFET's featuring excellent threshold voltage control in low-power applications

Tadahiro Ohmi, Hiroyuki Shimada, Y. Hirano, 1995, 1995 IEEE International SOI Conference Proceedings.

Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

Tadahiro Ohmi, Mizuho Morita, T. Ushiki, 1997 .

Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications

Tadahiro Ohmi, T. Ushiki, Hisayuki Shimada, 1997 .