Ivan S. Kourtev

发表

Eby G. Friedman, Ivan S. Kourtev, E. Friedman, 2000, The VLSI Handbook.

Delay Insertion Method in Clock Skew Scheduling

Baris Taskin, Ivan S. Kourtev, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

Alex K. Jones, Raymond R. Hoare, Ivan S. Kourtev, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

The sandbox design experience course

Narayanan Vijaykrishnan, David L. Landis, Ivan S. Kourtev, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

Alex K. Jones, Raymond R. Hoare, Ivan S. Kourtev, 2006, FCCM.

Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking

Baris Taskin, Ivan S. Kourtev, John Wood, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Demonstration of Speed and Power Enhancements through Application of Non-Zero Clock Skew Scheduling

Eby G. Friedman, Dimitrios Velenis, Kevin T. Tang, 2000 .

Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits

Baris Taskin, Ivan S. Kourtev, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Noise immunity of digital circuits in mixed-signal smart power systems

Eby G. Friedman, Radu M. Secareanu, Ivan S. Kourtev, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

A 64-way VLIW/SIMD FPGA architecture and design flow

Alex K. Jones, John Foster, Raymond R. Hoare, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits

Eby G. Friedman, Ami Litman, Ivan S. Kourtev, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits

Baris Taskin, Ivan S. Kourtev, 2009, J. Circuits Syst. Comput..

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling

Eby G. Friedman, Dimitrios Velenis, Kevin T. Tang, 2002, J. Circuits Syst. Comput..

Short Courses in System-on-a-Chip (SoC) design

Donald M. Chiarulli, Steven P. Levitan, Bruce R. Childers, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Linear timing analysis of SOC synchronous circuits with level-sensitive latches

Baris Taskin, Ivan S. Kourtev, 2002, 15th Annual IEEE International ASIC/SOC Conference.

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2002, TAU '02.

Reduced dynamic swing domino logic

Ivan S. Kourtev, Roy Mader, 2003, GLSVLSI '03.

Advanced timing of level-sensitive sequential circuits

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Efficient CAD development for emerging technologies using Objective-C and Cocoa

Alex K. Jones, Ivan S. Kourtev, Bryan A. Brady, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Delay insertion method in clock skew scheduling

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Clock skew scheduling for improved reliability via quadratic programming

Eby G. Friedman, Ivan S. Kourtev, E. Friedman, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Performance metrics for asynchronous digital circuits applicable to computer-aided design

Ivan S. Kourtev, Rajani Parthasarthy, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

LURU: global-scope FPGA technology mapping with content-addressable memories

Alex K. Jones, Raymond R. Hoare, Ivan S. Kourtev, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Substrate coupling in digital circuits in mixed-signal smart-power systems

Eby G. Friedman, Radu M. Secareanu, Scott Warner, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Performance improvement of edge-triggered sequential circuits

Baris Taskin, Ivan S. Kourtev, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..