H. van der Ploeg

A 3.3 V 10 b 25 Msample/s two-step ADC in 0.35 /spl mu/m CMOS

R. Remmers, H. van der Ploeg, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications

H. van der Ploeg, M. Vertregt, M. Lammers, 2006, IEEE Journal of Solid-State Circuits.

A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS

B. Buter, H. van der Ploeg, M. Vertregt, 2008, 2008 IEEE Symposium on VLSI Circuits.

A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications

H. van der Ploeg, M. Vertregt, M. Lammers, 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-/spl mu/m CMOS

A. Zjajo, H. van der Ploeg, M. Vertregt, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).