Fumiyasu Hirose

发表

Performance evaluation of an event-driven logic simulation machine

Fumiyasu Hirose, F. Hirose, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Behavioral design and test assistance for pipelined processors

Fumiyasu Hirose, Tsuneo Nakata, Hiroaki Iwashita, 1992, Proceedings First Asian Test Symposium (ATS `92).

Integrated Design and Test Assistance for Pipeline Controllers (Special Issue on VLSI Testing and Testable Design)

Fumiyasu Hirose, Tsuneo Nakata, Hiroaki Iwashita, 1993 .

Acceleration of behavioral simulation on simulation specific machines

Fumiyasu Hirose, Minoru Shoji, Hiroshi Nagai, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Acceleration of mincut partitioning using hardware CAD accelerator TP5000

Fumiyasu Hirose, Shintaro Shimogori, Masahiro Sano, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

An approach to verify a large scale system-on-a-chip using symbolic model checking

Fumiyasu Hirose, Tsuneo Nakata, Koichiro Takayama, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Panel: New Research Problems in the Emerging Test Technology

Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, 1995, Asian Test Symposium.

A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

Fumiyasu Hirose, Nobuaki Kawato, Koichiro Takayama, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Logic simulation system using simulation processor (SP)

Kenji Iwata, Fumiyasu Hirose, Nobuaki Kawato, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

Simulation processor "SP"

Fumiyasu Hirose, Hiroshi Yamada, Tatsuya Shindo, 1989, Syst. Comput. Jpn..

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006

Fumiyasu Hirose, 2006, ASP-DAC.

Automatic program generator for simulation-based processor verification

Fumiyasu Hirose, Tsuneo Nakata, Hiroaki Iwashita, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

CTL model checking based on forward state traversal

Fumiyasu Hirose, Tsuneo Nakata, Hiroaki Iwashita, 1996, Proceedings of International Conference on Computer Aided Design.

Automatic test program generation for pipelined processors

Fumiyasu Hirose, Tsuneo Nakata, Hiroaki Iwashita, 1994, ICCAD.

A test generation system using a logic simulation engine

Fumiyasu Hirose, Nobuaki Kawato, Koichiro Takayama, 1991 .

Test pattern generation system for delay faults using a high speed simulation processor 'SP'

Fumiyasu Hirose, Yukiko Izuta, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Speeding Up Look-up-Table Driven Logic Simulation

Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose, 1999, VLSI.

A high-speed test-generation method using a test generation circuit

Fumiyasu Hirose, Nobuaki Kawato, Koichiro Takayama, 1990, Systems and Computers in Japan.

Proceedings of the 24th Asia and South Pacific Design Automation Conference

Fumiyasu Hirose, 2019, ASPDAC.

Efficient Placement and Routing Techniques for Master Slice LSI

Fumiyasu Hirose, Hiroshi Shiraishi, 1980, 17th Design Automation Conference.

Automatic Test Program Generation For Pipelined Processors

Fumiyasu Hirose, Tsuneo Nakata, Hiroaki Iwashita, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Logic synthesis for a single large look-up table

Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Topologically flexible and highspeed network (ToF-Net)

Fumiyasu Hirose, Hiroshi Matsuoka, S. Shimogori, 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.